With decreasing gate lengths in metal oxide semiconductor field effect transistors (MOSFET), thin dielectrics are necessary to increase drive current and improve short channel behavior.
Conventional methods for forming high-k dielectrics include chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). For ultra-thin high-k gate dielectric formation, physical vapor deposition methods have fallen into disfavor, as they typically damage the deposition surface during sputtering. Alternatively, chemical vapor deposition (CVD) and atomic layer deposition (ALD) are substantially damage free processes, in which good step coverage is provided with less particle generation than physical vapor deposition (PVD).
Prior forming methods have been unsuccessful in providing continuous and uniform ultra-thin high-k gate dielectric layers. The term “ultra-thin” denotes a high-k gate dielectric layer having a thickness on the order of about 15 Å or less. Atomic layer deposition (ALD) and chemical vapor deposition (CVD) fail to provide uniform gate dielectric layers, since atomic layer deposition and chemical vapor deposition typically result in non-uniform nucleation when utilized to deposit ultra-thin dielectric layers. Non-uniform nucleation results from the complex bonding of metal organic or metal halide precursors, which are utilized in CVD and ALD processes. The complex bonding of metal organic or metal halide precursors acts as an obstruction to full saturation of the deposition surface. For example, hafnium chloride precursors comprise hafnium bonded with four chlorides, and when the hafnium of the precursor bonds to a silicon-containing surface of a substrate the bonded chlorides can block up to 10 bonding sites of the substrate, resulting in non-uniform nucleation. In ultra-thin film deposition, non-uniform nucleation produces a non-continuous layer resulting in islands of deposited dielectric material. Non-continuous dielectric layers incorporated within gate dielectrics typically result in leakage effects, which reduce device performance.
Gate dielectric and gate electrode material and structure should posses a number of properties to be useful for state-of-the-art MOSFET devices. First, the gate dielectric should be “electrically thin” when the gate is biased in inversion creating a large surface density of mobile inversion charge in the transistor channel. The term “electrically thin” denotes a high capacitance per unit area. In turn, the gate dielectric capacitance in inversion consists of several parts including the capacitance of the dielectric material itself and the so-called depletion capacitance of the adjacent gate electrode. In order to make the gate dielectric electrically thinner, one would (1) physically thin down gate dielectrics, (2) select gate dielectric materials with higher dielectric permittivity (“high k” materials), and (3) choose gate electrodes adjacent to the gate dielectric with a smaller depletion region.
Second, the entire gate structure including FET channel region, gate dielectric, and gate electrode should be able to support a FET with a low threshold voltage from about 0.1V to about 0.4V. While a desired threshold voltage can be achieved by varying channel doping and selecting the optimum work-function for the gate electrode, the threshold voltage can be inadvertently altered by the presence of a large fixed and/or trapped charge at both the gate dielectric interface and within the dielectric itself. Further, the density of trapped and/or fixed charge can be inadvertently altered by exposure to a high-temperature (e.g., a 1000° C. junction activation anneal) or during FET operation. Accordingly, it is highly desirable to minimize the total surface density of such fixed and/or trapped charge to prevent any undesirable shifts in threshold voltage. Typically, the total surface density of fixed and/or trapped charge is kept below 8×10−7 C·cm−2 or, equivalently, the surface number density of charged sites is kept below about 5×1012 cm−2 for a single charged site. A charge density of 8×10−7 C·cm−2 shifts the threshold voltage by about 0.4 V for a gate dielectric with capacitance per unit area in inversion of about 2×10−6 F·cm−2.
Third, the gate electrode structure should not impede charging/discharging of the layer directly adjacent to the gate dielectric, for the speed of such charging/discharging is directly related to the speed of FET switching. Presence of multiple layers in the gate electrode can adversely affect the speed of the gate electrode charging due to the presence of a large interface or contact resistance between the adjacent conductive layers.
Accordingly, it is desirable to keep the interface or contact resistance between the layers in the gate electrode below about 1×10−6 Ω·cm2, more preferably to below 3×10−7 Ω·cm2. Indeed, it would take an extra 2 picoseconds to charge a gate dielectric capacitance of about 2×10−6 F·cm−2 through an additional interface resistance of 1×10−6 Ω·cm2. In addition, the extra charging time associated with the interface resistance can further increase due to an extra parasitic capacitance present at the gate corners below the resistive interface. The gate-to-drain parasitic capacitance can be further multiplied by about a factor of two due to a Miller feedback effect. For short channel transistors with the physical gate length of less than about 40 nm, such extra capacitance can be as large as the gate capacitance itself, effectively doubling extra charging time. The fastest state-of-the-art CMOS circuit (a ring oscillator) has switching time per stage of about several picoseconds enabling more complex circuits operating with electrical pulses as short as 30-100 picoseconds. Therefore, a resistive interface in the gate electrode with interface/contact resistance of more than of 1×10−6 Ω·cm2 may introduce a substantial extra delay and/or undesirably change the shape of electrical pulse.
High-k based gate dielectrics are competing with conventional silicon oxynitride based dielectrics. Silicon oxide or oxynitride has been a gate dielectric material of choice for more than 30 years. Prior oxynitride based gate dielectrics have (a) a physical thickness of about 1 nm, (b) a capacitance per unit area in inversion of about 2×10−6 F·cm−2 for a doped polysilicon gate electrode and about 2.2×10−6 F·cm−2 for a metallic gate electrode, (c) gate tunneling or leakage current of about 200 A/cm2 at 0.8V gate bias, and (d) a fixed or trapped charge of less than 2×10−7 C·cm−2. It is desirable that a high-k gate dielectric provides a similar or higher capacitance per unit area at a lower gate tunneling or leakage current with an acceptable amount of fixed or trapped charge as alluded above. In addition, a highly preferred high-k gate dielectric provides greater than approximately a 10% increase in the gate capacitance in inversion in comparison to similar oxynitride-based gate dielectrics.
Typical high-k based dielectrics known in the art are comprised of insulating metal oxides such as hafnium oxide (HfO2) and zirconium oxide (ZrO2). In these compounds, a metal-oxygen bond is easily polarizable under an external electric filed yielding a high dielectric constant (high-k). The very same high polarizability of these bonds results in highly undesirable scattering of channel mobile charges by remote phonons present in the high-k material. As the result, the transistor drive current can be substantially reduced by the presence of high-k materials in the gate insulator. Several existing solutions are directed to the reduction of the scattering problem. In one known solution, a silicon material is added to the metal oxide creating a ternary insulating compound known as metal silicate. While a metal silicate creates less scattering by remote phonons, the dielectric constant of metal silicates is typically substantially lower than that of a pure metal oxide. Consequently, a layer of metal silicate should be substantially thinner than that of a pure metal oxide.
In an alternative solution, a layer of silicon oxide or silicon oxynitride is disposed between the channel and the high-k layer. The remote phonon scattering is then reduced because the high-k layer is positioned further away from the channel. It is desirable that the silicon oxynitride layer be thinner than current state-of-the-art silicon-oxynitride-based gate dielectrics in order for such high-k stack to have acceptable gate capacitance as alluded above.
While there are multiple ways of forming metal-oxide-based high-k layers, all of them employ oxidation of metal atoms at the wafer surface by exposing the surface to an oxygen-containing precursor. In one set of methods, the high-k layer is simply deposited from metal and oxygen containing precursors. In another set of methods, the metal layer is first formed on the surface and then oxidized by an oxygen precursor.
One major drawback of prior forming methods for producing metal-oxide-based high-k layers, in which the metal layer is first formed on the surface and then oxidized by an oxygen precursor, is that oxidation of metal competes with the oxidation of semiconductor (silicon) yielding thick insulating film adjacent to the semiconductor with a dielectric constant of below 10. Alternatively, at much reduced overall oxidation rate (e.g., at a low partial pressure of oxidation precursor and/or at a low oxidation temperature), partial oxidation of metal occurs leading to highly undesirable spatial variation of gate dielectric properties such as its' tunneling current, fixed or trapped charge, etc.
In view of the prior art mentioned, there is a need for providing an improved gate stack, which contains a metallic electrode and a high-k dielectric.